In an integrated circuit or a system-on-chip (SoC), a power supply network is provided to supply the components in the circuit with power from an external power supply. A conventional power supply network consists of a power network and a ground network.
A power supply network is characterized by its structure or topology, i.e. metal layers used, grid structure versus tree structures or combinations of these, distances between wires and/or grid meshes, and the width of the wires. Supply pads and a peripheral supply ring surrounding the internal grid structure are also considered to be part of the power supply network.
Power integrity is a key parameter in characterising and controlling integrated circuit and SoC functionality and performance. The decreasing component sizes in deep sub-micron technologies allows packing densities to be increased with more functional blocks in an integrated circuit, with the supply and threshold voltages in the circuit being reduced accordingly. On the other hand, the switching current and switching speed increase. A consequence of decreasing the supply voltage is that the acceptable level of voltage drop in the power supply network also decreases. However, the actual voltage drop increases due to increased resistance in the power supply network from thinner wires, and increased supply current levels. A similar effect to voltage drop in the power network occurs in the ground network, and is called voltage rise. Voltage drop in the power supply network comprises both voltage drop in the power network and voltage rise in the ground network.
One conventional way of reducing the voltage drop (otherwise known as the IR-drop, from V=IR) across the power supply network for an integrated circuit is to widen all of the wires of the power supply network. This results in the resistance of these wires being reduced. However, this also uses routing resources which could otherwise be used for signal and clock wires.
In reducing the IR-drop to specified limits, the area occupied by the supply grid in an SoC is increased to such proportions that it seriously impacts the available routing resources for data and clock signals. In many designs, the supply grid requires an extra metal layer, which increases production costs. The area required by the supply grid can be reduced if the supply grid is made with narrower wires and if a larger width (and hence lower-resistance) peripheral supply ring is applied around the supply grid. However, the penalty is SoC area. Instead of an area-consuming peripheral supply ring, an increased amount of supply pads can be applied if there is space in the input/output ring. However, the SoC package costs will be increased. If there is no space in the input/output ring, adding supply pads will also increase SoC area.
U.S. Pat. No. 5,767,011 describes a fabrication method for integrated circuits and a resulting structure. The method includes adding power lines and/or increasing the width of power lines and/or adding a power bus near regions of high current flow.